module LED_BLINK(input clk_aux,
					  output [7:0] led							
    );



reg [31:0] ClkDivCounter;
reg OnePPS;
reg [7:0] LED_Counter;

assign led = LED_Counter;

//FPGAs like everything to de done synchronous to a master clock.
//To do a divider for our one pulse per second,  Let's 
//create a 1 clock wide pulse when our divider counter rols over

always @(posedge clk_aux)
begin
	if(ClkDivCounter >= (20000000))
		begin
			ClkDivCounter<=0;
			OnePPS <= 1;
		end
	else
		begin
			ClkDivCounter <= ClkDivCounter + 1;
			OnePPS <= 0;
		end
end

//We will clock out LEd counter at the master clock rate but
//use the OnePPS signal as out clock enable.  

always @(posedge clk_aux)
begin
	if(OnePPS == 1)
		LED_Counter <= LED_Counter + 1;
end



endmodule
